1. Field of the Invention
The present invention relates to a fabrication method of a high-speed dual-gate CMOSFET with high reliability.
2. Description of the Related Art
Recently, the fineness of the gate length of a MOSFET has been reduced to approximately 0.1 xcexcm, as large-scale integrated circuits have become highly integrated. The finer gate length increases a transconductance (gm), resulting in a shorter delay time. Consequently, a MOSFET can operate at a higher speed.
In order to make a normally operating MOSFET having a fine gate, and in particular, a PMOSFET, it is important to suppress a short channel effect. For a PMOSFET having a fine gate, a surface channel (SC) type MOSFET including a gate electrode of P+ polysilicon has become common, rather than a buried channel (BC) type MOSFET including a gate electrode of N+ polysilicon, which was widely used conventionally.
A CMOSFET in which an N+ polysilicon gate electrode is used an NMOSFET while a P+ polysilicon gate electrode is used in PMOSFET is called a dual-gate CMOSFET.
An exemplary fabrication method of the dual-gate CMOSFET is described by K. F. Lee et al., in xe2x80x9cIEDM Tech. Dig.xe2x80x9d (1993), p. 131. FIGS. 1A-1E and 2F-2H are diagrams schematically showing processes of this method. In FIGS. 1A-1E and 2F-2H the NMOSFET is shown the left side while the PMOSFET is shown on the right side.
In accordance with this method, a recessed LOCOS (Local Oxidation of Silicon) film 122 of 750 nm thickness is formed on a silicon substrate 121 using a known technique. A P well 123a and an N well 123b are then formed using a high-energy ion implantation apparatus. In this example, the P well 123a is formed by implanting boron (B) of 1xe2x89xa71013 cmxe2x88x922 with 400 keV, and the N well 123b is formed by implanting phosphorus (P) of 1xe2x89xa71013 cmxe2x88x922 with 900 keV (FIG. 1A).
Next, a resist pattern is formed (not shown), to be used as a mask for defining an ion implantation region. Using the resist pattern as the mask, punchthrough suppression implantation for suppressing the short channel effect, and channel implantation for controlling a threshold voltage are performed by ion, implantation, only in regions 124a, 124b that are to be positioned under gates.
For example, the punchthrough suppression-implantation and the channel implantation for the P well are performed in the region 124a by implanting boron of 4xe2x89xa71012 cmxe2x88x922 with 45 keV and boron fluoride (BF2) of 1xe2x89xa71013 cmxe2x88x922 with 90 keV.
On the other hand, the punchthrough suppression implantation and channel implantation for the N well are performed in the region 124b by implanting phosphorus (P) of 4xe2x89xa71012 cmxe2x88x922 with 120 keV and arsenic (As) of 1xe2x89xa71013 cmxe2x88x922 with 100 keV (FIG. 1B).
A gate oxidation film 125 is then formed with a thickness of 4 nm, in a furnace at 800xc2x0 C. On the gate oxidation film 125, a polysilicon film 126 having a thickness of 200 nm and a silicon nitride film 127 having a thickness of 100 nm are deposited by LPCVD, and thereafter a resist pattern (not shown) to be used as a mask for patterning gate electrodes is formed.
Using the resist pattern as the mask, unnecessary portions of the polysilicon film 126 and the silicon nitride film 127 are etched away, thus forming polysilicon gate electrodes 126, each having a gate length of about 0.1 xcexcm (FIG. 1C).
Next, a resist is formed (not shown), for preventing ion implantation into undesired portions. Using the thus formed resist pattern as the mask, As of 5xc3x971014 cmxe2x88x922 is introduced by ion implantation at 10 keV to form a shallow junction source and drain of the NMOSFET (shallow junction S/D) 128a (FIG. 1D).
After an SiO2 film having a thickness of 50 nm is deposited using TEOS by CVD, the SiO2 film is etched back by reactive ion etching (RIE) to form first side walls 129. A resist pattern (not shown) for preventing ion implantation into undesired portions is then formed. Using the resist pattern, BF2 of 1xe2x89xa71015 cmxe2x88x922 is introduced with 10 keV to form a shallow junction source and drain 128b of the PMOSFET (FIG. 1E).
Next, SiO2 film having a thickness of 200 nm is deposited again using TEOS by CVD, following which the SiO2 film is etched back by reactive ion etching (RIE), to form second side walls 130 (FIG. 2F).
Then, deep junction S/Ds 131a, 131b are formed by ion implantation. The deep junction source and drain 131a of the NMOSFET are formed by implanting As of about 5xe2x89xa71015 cmxe2x88x922 with 20 keV while the deep junction source and drain 131b of the PMOSFET are formed by implanting BF2 of about 5xe2x89xa71015 cmxe2x88x922 with 10 keV.
Simultaneously, impurities such as As or BF2, are also introduced into the polysilicon gate electrodes 126. More specifically, As is introduced into the gate electrode of the NMOSFET so that an N+ polysilicon gate electrode 126a is obtained. On the other hand, BF2 is introduced into the gate electrode of the PMOSFET so that a P+ polysilicon gate electrode 126b is obtained (FIG. 2G).
Annealing is then performed for 10 seconds at 1050xc2x0 C. by a rapid annealing apparatus (RTA) and then drive-in is performed in a typical electric furnace at 800xc2x0 C. for 20 minutes, thus producing a dual-gate CMOSFET having a fine gate length (FIG. 2H).
As mentioned above, the CMOSFET which includes an NMOSFET having an N+ polysilicon gate electrode, and a PMOSFET having a P+ polysilicon gate electrode is fabricated by introducing the same impurities into the gate electrodes as those introduced into the source and the drains during the S/D ion implantation. The CMOSFET thus fabricated can withstand the short channel effect, operate at a high speed and have a high reliability.
The thus fabricated CMOSFET, however, has a problem where the threshold voltage may vary because of penetration of boron (B) included in P+ polysilicon, into the channel region, through the gate oxidation film during the annealing process.
In order to avoid penetration of boron (B), the following three methods can be considered.
(1) Only boron is used as the impurity introduced into the source and the drain.
(2) The annealing process is performed at a lower temperature.
(3) A film to which nitrogen (N) is added is used as the gate oxidation film.
Regarding method (1), the penetration of boron (B) frequently occurs when boron fluoride (BF2) is implanted into the gate electrode. In other words, when just boron is implanted, penetration of boron does not occur as long as the temperature is kept relatively low or the concentration of boron is kept low. Therefore, it can be considered that boron is introduced by boron implantation. In this case, however, the junction of the S/D becomes deeper when boron is implanted into both the source and the drain simultaneously because boron is a light element. This makes the resultant MOSFET inappropriate for a MOSFET having a fine gate length.
Implantation with an energy level of 1 keV or less or implantation using decaborane (B10H16), which is a heavy element including no fluorine (F), has recently attracted attention. Such implantation, however, requires a special ion implantation apparatus, thus increasing the fabrication cost. In addition, it is difficult to immediately apply such implantation to the fabrication process because the development of such implantation technology is relatively recent.
Regarding method (2), even if boron fluoride (BF2) is used, the penetration of boron through the gate oxidation film does not cause fluctuation of the threshold voltage, as long as the annealing process is performed at a relatively low temperature and for a short time period. According to the experiments by the inventors of the present invention, in a case of the gate oxidation film having a thickness of 35 angstroms, the threshold voltage fluctuated when the annealing process was performed at 1050xc2x0 C. for 10 seconds, whereas it did not fluctuate when the annealing process was performed at 1000xc2x0 C. for 10 seconds.
However, when the temperature of the annealing process is decreased from 1050xc2x0 C. to 1000xc2x0 C., depletion occurs in the N+ polysilicon gate electrode. This results in a decrease of the transconductance (gm) and the ON current of the NMOSFET by about 10%.
Regarding method (3), in a case of using oxidized nitride film, which is a gate oxidation film with nitrogen added thereto, no fluctuation of the threshold voltage due to penetration of boron through the gate oxidation film occurs, even if BF2 is used. However, it is known that the addition of nitrogen (N) causes generation of fixed charges and an interface state at the interface between silicon and the gate oxidation film including nitrogen, resulting in fluctuation of the threshold voltage and decrease of transconductance.
It is reported that the problems of the fixed charges and the interface state can be improved by improving the method for adding nitrogen. However, the gate oxidation film including nitrogen is inferior to the gate oxidation film formed by thermal oxidation.
As described above, methods (1) to (3) are unable to provide a fabrication method of a dual-gate CMOSFET capable of fabricating a dual-gate CMOSFET having the desired performance at a low cost.
Therefore, it is an object of the present invention to provide a fabrication method which enables easy fabrication of a dual-gate CMOSFET, having a satisfactory performance with high precision at a cost appropriate for industrial mass-production.
In order to achieve the above object, a fabrication method for fabricating a dual-gate CMOSFET on a semiconductor substrate according to the present invention, includes: implanting ions of N-type impurity for forming a deep junction source and drain in a first region on the semiconductor substrate where an NMOSFET is to be formed; performing a first annealing process for activating the N-type impurity; implanting ions of P-type impurity for forming a deep junction source and drain in a second region on the semiconductor substrate where a PMOSFET is to be formed; and performing a second annealing process for activating the P-type impurity.
In one embodiment of the present invention, the first annealing process is performed using a rapid anneal apparatus at a temperature of 1050xc2x0 C. or higher.
In another embodiment of the present invention, the second annealing process is performed using a rapid anneal apparatus at a temperature of 1000xc2x0 C. or lower.
Thus, in accordance with the fabrication method for fabricating the CMOSFET of the present invention, the annealing process for activation is performed at a high temperature of 1050xc2x0 C. or higher, after ion implantation, to form the deep junction S/D of the NMOSFET, and thereafter the annealing process for activation is performed at a low temperature of 1000xc2x0 C. or lower, after ion implantation, to form the deep junction S/D of the PMOSFET. Therefore, As in the gate electrode of N+ polysilicon of the NMOSFET is activated sufficiently, thus preventing, the problem of depletion. Also, the fluctuation of the threshold voltage due to penetration of boron included in the gate electrode, through the gate oxidation film, can be prevented in the PMOSFET.
This summary of the invention does not necessarily describe essential features so that the invention may also be a sub-combination of these described features.